The present invention relates to logic switching circuitry which employs MOSFET devices and more particularly to an improved high efficiency, high current inverter buffer circuit for integrated circuits.
Digital data processing systems have been fabricated as large-scale integrated (LSI) circuits using metal-oxide-semiconductor field effect transitor (MOSFET) technology for some time.
One of the major disadvantages heretofore associated with MOSFET circuits has been the relatively large number of supply voltages, and the relatively high magnitude of supply voltages required to operate the circuit efficiently. The higher number of supply voltages increases the complexity of the external circuitry associated with the MOS integrated chips, and also increases the number of pins required to interface the integrated circuit package with the external circuitry. The higher voltage results in greater power dissipation and requires larger geometries to provide the necessary voltage breakdown characteristics.
One of the fundamental circuits required in a MOSFET integrated circuit is an inverter buffer to drive a load in which a resistive type load interconnects the drain voltage to the inverter output and an enhancement mode transistor connects the output to the source voltage. When the enhancement mode transistor is switched off, the output is at drain voltage, which is typically referred to as the logic or binary "1" level. When the enhancement mode transistor is switched on, the output is pulled down to a level near the source voltage, which is typically referred to as the binary or logic "0" level. The logic "0" level depends on the relative resistance of the enhancement mode transistor to that of the resistive type load. Although the use of a simple resistor as the load has the advantage that one of the output levels is the drain supply voltage, the circuit is not practical in integrated circuit form because a diffused region having a resistance sufficiently large to provide a low level of power dissipation occupies a prohibitively large area.
One substitute for a diffused load resistor is an enhancement mode transistor in which the gate is connected to the drain supply voltage. However, this circuit has the disadvantage that the logic "1" level of the output can reach a potential equal only to the drain voltage V.sub.D less the threshold voltage V.sub.T of the load transistor, which is typically several volts. Another disadvantage is that the output current of the load device decreases very rapidly as the magnitude of the voltage on the output, which is the source voltage of the load transistor, increases.
These objections to the use of an enhancement mode transistor as a load can be remedied by applying a voltage V.sub.G to the gate of the transistor of greater magnitude than the drain voltage, but this requires an additional supply voltage. In addition, such a circuit exhibits undesirable nonlinearity in the output current of the inverter circuit because as the output voltage approaches drain voltage, both the source to drain voltage and the source to gate voltage of the load transistor decreases.
The logic "1" level at the output of the inverter circuit can be raised to V.sub.D without the use of a higher gate voltage V.sub.G by means of a so-called boot strap inverter. However, the boot strap circuits require additional devices and have other disadvantages. Still another circuit which has been used is the complementary inverter having an n-channel enhancement mode transistor connected to the negative voltage supply and a p-channel enhancement mode transistor connected to the positive voltage supply, with the common drains being the output. The gates of the transistors are connected together and receive the input signal. When the input signal is negative, the n-channel enhancement mode device is turned off, the p-channel enhancement mode device is turned on, and the output is at the level of the positive supply voltage. When the input signal is positive, the n-channel device is on, the p-channel device is off, and the output is at the level of the negative supply voltage. Such a complementary inverter provides good switching characteristics and requires only one supply voltage. However, the use of both n-channel and p-channel devices requires an unusually large amount of area on an integrated circuit chip, and also requires several additional processing steps which significantly increases the cost of the circuit.
The inverter circuit shown in FIG. 1 and fully described in U.S. Pat. No. 3,775,693 comprises the depletion mode (D) MOS transistor Q1 connecting the drain supply voltage V.sub.D to the output of the circuit with the gate thereof being electrically coupled with the output. An enhancement mode (E) MOS transistor Q2 having the same type channel as transistor Q1 provides a path connecting the output of the circuit to a source voltage supply V.sub.S illustrated as ground. The gate of transistor Q2 forms the input to the inverter circuit. The inverter circuit of FIG. 1 is useful for both p-channel and n-channel integrated circuits, and has the advantage of providing an output logic "1" level when the enhancement mode device transistor Q2 is switched off that is substantially equal to the drain supply voltage, thus requiring only one voltage supply. Transistor Q2, when switched on, pulls the output down to the source supply voltage V.sub.S. The advantage of this circuit is its simplicity. The disadvantage is that the circuit operates in class A operation, that is, it constantly draws the same amount of current in its pull-up condition. The enhancement device transistor Q2 in order to pull down the output to logic "0" has to carry the current from the outside and also the current carried by the depletion device transistor Q1. An enhancement device having the same size as a depletion device carries less current than the depletion device and, as a result, the enhancement device must be made quite large to carry the current of the depletion device and thereby requires a large amount of area on an integrated circuit chip.
FIG. 2. discloses another prior art circuit disclosed in the above cited patent incorporating the circuit of FIG. 1 and having added thereto to improve its performance a push-pull output stage comprising a pair of transistors Q3 and Q4 connected in series between the drain voltage V.sub.D and the source voltage V.sub.S. Transistor Q4 connected to the source voltage is an enhancement mode device, and transistor Q3 connected to the drain voltage is preferably a depletion mode device. The output from the basic inverter stage, including transistors Q1 and Q2, is coupled to the gate of the depletion mode transistor Q3 and the gate of the enhancement mode transistor Q4 is connected to the logic input to the basic inverter stage. The output of the basic circuit of transistors Q1 and Q2 will turn off transistor Q3 when the output has to be low, therefore, removing the necessity of the transistor Q4 from having to carry the current passing through transistor Q3. When the output is to go high, the gate of transistor Q3 is driven high with very little delay (delay of transistors Q1 and Q2) making its gate to source voltage positive causing very strong conduction and, thereby, shortening the rise time at the output.